Design of Low-Voltage and low-Power inverter based Double Tail Comparator

Design of low voltage double-tail Comparator with pre-amplifier and latching stage is reported in this paper. Design has specially concentrated on delay of both single tail comparator and double-tail comparator, which are called clocked regenerative comparator. Based on a new dynamic comparator is proposed, where the circuit of conventional double tail dynamic comparator is modified for low power and fast operation even in small supply voltages. Simulation results in 0.25μm CMOS technology confirm the analysis results. It is shown that proposed dynamic comparator both power consumption and delay time reduced. Both delay and power consumption can be reduced by adding two NMOS switches in the series manner to the existing comparator. The supply voltages of 1.5V while consuming 15μw in proposed comparator and 16 μw in existing comparator respectively. Keywords-Conventional dynamic comparator, double tail comparator, Proposed dynamic comparator, low power, fast operation, low power, Delay.